42 Gb/mm2: Micron Sets Density Target for 2027 NAND

Micron targets a storage density of approximately 42 gigabits per square millimeter for its next-generation NAND flash, a figure that represents a doubling of the capacity found in its current products. The company, which operates in the competitive memory chip market, announced these specifications during an industry event held this week. The new product line, designated as G11, is scheduled to enter mass production in the second half of 2027.

The shift from the current G9 generation to G11 involves specific technical upgrades across several metrics. I/O speeds are projected to increase by up to 50%, moving from 3,600 megatransfers per second to 5,400 megatransfers per second. Additionally, the energy required to transfer each bit of data should decrease by more than 25%. These improvements are intended to support high-capacity solid-state drives for both client devices and data centers, as well as storage solutions designed for artificial intelligence workloads that require higher bandwidth and lower power consumption.

The primary engineering change enabling these gains is the adoption of wafer-on-wafer bonding. This technique allows the company to manufacture the memory array and the peripheral circuitry on separate wafers, each optimized for its specific function, before bonding them together. While Micron has utilized CMOS-under-array designs in previous generations, this bonding approach provides greater flexibility to optimize the memory and logic components independently. Chinese competitor YMTC has already employed this method.

Scott DeBoer, who serves as president and chief technology and products officer at Micron, confirmed that the timing for this technology is appropriate. "This is the right timing for that technology," DeBoer stated, describing G11 as the most advanced NAND in the world. He noted that the company had previously pledged to introduce the technology once it became cost-effective and relevant to product specifications.

The G11 design will also feature more than 400 layers, although the company has not disclosed the exact number of active wordlines or memory decks. Micron stated that the design will feature an industry-leading memory cell pitch, suggesting that the density increase results from both additional layers and smaller cell dimensions. The company plans to reveal further technical details in 2027 as high-volume production approaches.

Looking beyond G11, Micron indicated it will continue scaling in all three dimensions rather than relying solely on layer count. The company is developing high-mobility materials and ultra-dense cell architectures to improve transistor characteristics and reduce energy usage. DeBoer stated that the roadmap includes a focus on new materials and densifying cell architecture, noting that both the industry and Micron are scaling by adding layers and shrinking cell dimensions.