Chinese chipmakers stack exposure steps to bypass EUV controls

Export controls have restricted Chinese access to extreme ultraviolet lithography tools, forcing manufacturers to rely on older deep ultraviolet equipment for advanced chip production. This shift alters the economic and technical baseline for domestic semiconductor output.

ASML remains the sole producer of EUV machines, which use 13.5nm wavelength light to print fine features on processors. Analysts estimate the technological gap between China and Western rivals is at least five years. Despite this barrier, Chinese firms have continued advancing their manufacturing capabilities using alternative methods.

A 2023 teardown of the Huawei Mate 60 Pro revealed that SMIC produced the Kirin 9000S processor using a 7nm-class process without EUV. More recent analysis suggests SMIC has refined its DUV-based process to approach 5nm density, though it still lags behind TSMC and Samsung. The primary technique involves multiple patterning, where manufacturers split complex designs into several simpler patterns and build layers incrementally.

Chris Mack, co-founder and CTO of Fractilia, explains that industry standards previously held three exposures on a 193 immersion tool to be cost-equivalent to one EUV exposure. However, when manufacturers require four masks, EUV becomes the cheaper option. Each additional exposure increases the risk of alignment errors and process variation. Designers often add space around features to compensate, which enlarges the chip and reduces the number of dies per wafer. Mack noted, "You don't sell wafers, you sell die," emphasizing the financial impact of reduced die counts.

Memory production illustrates this efficiency gap. A June report from Morgan Stanley estimated that CXMT produces only one-third as many bits per wafer as Western competitors. The bank described lithography access as a hard ceiling for Chinese memory development. Mack added that node labels like 5nm or 3nm lack specific meaning without context, and SMIC's N+3 process remains less scaled than established 5nm processes from major rivals.

DUV technology still offers viable pathways for specific applications. Micron developed its 1-alpha DRAM without EUV by utilizing multiple patterning and tight process control. Morgan Stanley believes CXMT can achieve its planned move to 1-alpha DRAM for HBM3e without EUV. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to allow DUV use for the latest DRAM generations by the end of the decade. Mack stated that memory is much easier to produce without EUV than logic chips.

Even Micron eventually adopted EUV for its 1-gamma DRAM, which delivers over 30% greater bit density per wafer than its 1-beta generation. EUV presents its own challenges, such as stochastic effects that require higher exposure doses. Mack said he would be hard pressed to believe a 3nm or 2nm node could be economically viable without EUV.

Chinese chipmakers can continue expanding DUV capacity while accepting larger dies, poorer yields, or longer manufacturing times. Morgan Stanley projects CXMT will maintain its 1-alpha process without EUV but increase its global DRAM bit supply share from 14% in 2026 to 16% in 2028 through new capacity. The bank expects China's AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030.